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publication number s30ms-p_00 revision a amendment 8 issue date june 13, 2007 s30ms-p ornand tm flash family s30ms-p ornand tm flash family cover sheet s30ms01gp, s30ms512p 1 gb/512 mb, x8/x16, 1.8 volt nan d interface memory based on mirrorbit ? technology data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s30ms-p_00 revision a amendment 8 issue date june 13, 2007 distinctive characteristics ? single power supply operation ? 1.8 volt read, erase, and program operations ?v cc = 1.7 to 1.95v ? manufactured on 90 nm mirrorbit process technology ? bus widths - x8 and x16 ? page size ? full page read 2k + 64 byte ? partial page read 512 + 16 byte ? block (erase unit) architecture ? number of blocks 1gb: 1k blocks 512mb: 512 blocks ?block size 128k + 4k byte ? compatibility with nand flash i/o ? provides pinout and command set compatibility with single-power supply nand flash ? high-performance cache register ? cache register matches page size to improve programming throughput ? 100,000 program/erase cycles per sector typical ? 10-year data retention typical ? operating temperature ranges ? wireless (-25c to +85c) ? package options ? 48-pin tsop ? 137-ball fbga mcp compatible ? 100% valid blocks performance characteristics legend: b = bit, b = byte, k = 1024, m = 1048576 s30ms-p ornand tm flash family s30ms01gp, s30ms512p 1 gb/512 mb, x8/x16, 1.8 volt nan d interface memory based on mirrorbit ? technology data sheet (preliminary) read access times (maximum) full page random access 25 s partial page random access 8 s serial read 25ns current consumption (typical) read current 40 ma erase current 60 ma program current 60 ma standby current 10 ua read, program and erase performance (typical) x8 x16 program 2.3 mb/s 2.4 mb/s erase 2.7 mb/s 2.7 mb/s full page read 26.7 mb/s 40.1 mb/s partial page read 24.3 mb/s 34.9 mb/s
4 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 137-ball ms01gp mcp-compatible fbga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 ms01gp and ms512p 48-pin tsop pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 vbp137?137-ball fine pitch ball grid array (fbga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 48-pin tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. pin names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 capacitance (ta = 25c, f = 1 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.8 program and erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9. timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 id read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10. schematic cell layout and address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11. operation mode: logi c and command tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.2 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.3 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.4 page duplicate program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.5 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.6 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.7 status read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13. application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.1 power on/off sequence and power-on read enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.2 status read during a read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 5 data sheet (preliminary) figures figure 9.1 command input cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9.2 address input cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9.3 data input cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9.4 serial read cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9.5 status read cycle timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9.6 read cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9.7 column address change in read cycle timing diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . 21 figure 9.8 column address change in read cycle timing diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . 22 figure 9.9 program operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9.10 block erase timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9.11 cache program operation timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 figure 9.12 page duplicate program timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9.13 id read operation timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10.1 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12.2 column address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12.3 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12.4 serial input command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12.5 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12.6 page duplicate program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12.7 page duplicate program operat ion with random data input . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12.8 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12.9 multiple devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12.10 status read timing application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12.11 reset (ffh) command input during programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12.12 reset (ffh) command input during erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 figure 12.13 reset (ffh) command input during a read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12.14 reset (ffh) command during operations other than program, erase, or read . . . . . . . . 36 figure 12.15 status read command (70h) input after a reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13.1 power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13.2 power-on auto-read enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 13.3 status read during a read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 13.4 ry/by#: termination for the r eady/busy pin (ry/by#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13.5 wp# signal?low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) tables table 9.1 id byte settings summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9.2 4th id byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9.3 5th id byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10.1 memory addressing key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10.2 (1gb) x 8 device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10.3 (512mb) x8 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10.4 (1gb) x 16 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10.5 (512) x 16 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11.1 operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11.2 command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11.3 read mode operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12.1 page segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12.2 status output table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 7 data sheet (preliminary) 1. general description the s30ms-p is a 1.8v single voltage flash memory pr oduct manufactured using 90 nm mirrorbit technology. the s30ms01gp is a 1gb device, organized as 64m wo rds or 128mb. the s30ms512p is a 512mb device, organized as 32m words or 64mb. the s30ms-p family of devices offer advantages such as: ? fast write and sustained write speed su itable for data storage applications ? fast read speed and reliability suitable for demanding code storage applications ? proven mirrorbit technology the devices are offered in a 48-pin tsop, or fbga mcp-compatible packages. each device has separate chip enable (ce#) controls for the fbga package. the s30ms-p is a byte/word serial-type memory device that utilizes the i/o pins for both address and data input/output, as well as for command input. the er ase and program operations are automatically executed making the device most suit able for applications such as solid-state disks, pictures stor age for still cameras, cellular phones, and other systems that require high-density non-volatile data storage. typical application requirements are sh own in the table below with refe rence to the ornand capabilities. the devices include the following features: ? automatic page 0 read, allows access of the data in page 0 without command and address input of read command after power-up ? chip enable don't care support for direct connection with microcontrollers ? compatible with nand flash command set. commands are written to the device using standard microprocessor write timing. write cycles provide commands, addresses and data ? initiation of program and erase functions through command sequences. once a program or erase operation begins, the host system should only poll for status or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete ? manufactured using mirrorbit flash technology resulting in the highest levels of quality, reliability, and cost effectiveness application minimum requirements spansion ornand 2g network 14.4 kbps (1.8 kb/sec) 9 3g network 2 mbps (250 kb/sec) 9 3.5g network (hsdpa) 14.4 mbps (1.8 mb/sec) 9 full speed usb 1.5 mb/sec 9 mp3 playback 320 kbps (40 kb/sec) 9 mpeg2 (h.262) 3 mb/sec 9 mpeg4 (h.264) 1 mb/sec 9 wimax 0.25 mb/sec 9
8 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 2. connection diagrams 2.1 137-ball ms01gp mcp-compatible fbga pinout flash shared ornand flash do not use a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu dnu rfu rfu rfu vss rfu rfu rfu n-pre n-ale n-cle rfu rfu rfu rfu rfu rfu rfu rfu rfu n1-ce# rfu rfu rfu rfu rfu rfu dnu rfu rfu rfu rfu rfu rfu rfu rfu ry/by# rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu vss dq1 dq6 rfu rfu rfu rfu dnu dq15 dq13 dq4 dq3 dq9 rfu rfu rfu rfu dnu dq0 dq10 rfu n-vcc dq12 dq7 vss rfu rfu n-wp# dq14 dq5 rfu dq11 dq2 dq8 n-vcc rfu rfu rfu rfu vss rfu n2-ce# dnu rfu rfu rfu n-re# rfu rfu rfu rfu rfu rfu rfu rfu n-we# rfu rfu rfu rfu rfu rfu rfu rfu dnu rfu rfu legend
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 9 data sheet (preliminary) 2.2 ms01gp and ms512p 48-pin tsop pinout tsop-48 x8 x16 x16 x8 n.c n.c n.c n.c n.c n.c n.c n.c v cc v ss n.c n.c cle ale n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c pre v cc v ss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c v cc v ss n.c n.c cle ale n.c n.c n.c n.c v ss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 n.c pre v cc n.c n.c i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ry/by# re# ce# ry/by# re# ce# we# wp# we# wp# n.c n.c n.c
10 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 3. physical dimensions 3.1 vbp137?137-ball fine pitch ball grid array (fbga) 0.08 m mcab c c c 6 b 0.15 side view 137x 0.08 7 se e1 d1 10 9 8 6 4 5 2 1 3 e 7 e a corner pin a1 c d e f g h j k l m n 7 sd bottom view p c b a d e 0.15 (2x) c b c 0.15 (2x) 9 top view pin a1 corner a2 a index mark a1 0.10 3549 \ 16-038.25 \ 2.16.6 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbp 137 jedec n/a 13.00 mm x 11.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height a2 0.60 --- 0.76 body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 10.40 bsc. ball footprint e1 7.20 bsc. ball footprint md 14 row matrix size d direction me 10 row matrix size e direction n 137 total ball count b 0.35 0.40 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 11 data sheet (preliminary) 3.2 48-pin tsop 6 2 3 4 5 7 8 9 ts/tsr 048 mo-142 (d) dd 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 12.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n +1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b 3355 \ 16-038.10c
12 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 4. pin names and descriptions 4.1 pin names and functions 4.2 pin descriptions the device is a byte/word serial access memory that ut ilizes time-sharing input of address information. the device pin-outs are configured as shown in 137-ball ms01gp mcp-compatible fbga pinout on page 8 . pin name pin function i/o0 to i/o15 data input/output cle command latch enable ale address latch enable ce#, ce1#, ce2# chip enable re# read enable we# write enable wp# write protect pre power on read enable ry/by# ready/busy output v cc power v ss ground n.c. no connection pin description cle command latch enable : the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command register from the i/o port on the rising edge of the we# signal while ce# is low and cle is high. ale address latch enable : the ale signal is used to control loading of either address information or input data into the internal address/data register. address information is latched on the rising edge of we# if ce# is low and ale is high. input data is latched if ce# is low and ale is low. ce#, ce1#, ce2# chip enable : the device enters a low-power standby mode when the device is in ready mode. the ce# signal is ignored when the device is in a busy state (ry/by# = l), such as during a page buffer load or erase operation, and will not enter standby mode even if the ce# input goes high. the ce# signal may be inactive during the page buffer write and page buffer load of the array data. the 2gb device has two chip enable pins: ce1# and ce2# (one per die). we# write enable : the we# signal is used to control th e acquisition of data from the i/o port. re# read enable : the re# signal controls serial data output. data is available t rea after the falling edge of re#. the internal column address counter is also incr emented (address = address + 1) on this falling edge. i/o0 to i/o7 i/o port : the i/o0 to i/o7 pins are used as a port for tr ansferring address, command, and input/output data to and from the device. i/o8 to i/o15 i/o port : the i/o8 to i/o15 pins are used as a port for trans ferring input/output data to and from the device in x16 mode only. i/o8 to i/o15 pins must be low level during address and command input. wp# write protect : the wp# signal is used to protect the device from accidental programming or erasing. this signal is usually used for protecti ng the data during the power-on/off sequence when input signals are invalid. ry/by# ready/busy :the ry/by# output signal is used to indicate the operating condition of the device. the ry/by# signal is in busy state (ry/by# = l) during the program, erase, and read operations and return to ready state (ry/by# = h) after completion of the operation. the output buffer for this signal is an open drain. pre power-on read enable : the pre controls auto read operation executed during power-on. the power-on auto- read is enabled when pre pin in tied to v cc . v ss ground : v ss is the ground. n.c no connection : lead is not internally connected.
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 13 data sheet (preliminary) 5. block diagram 6. absolute maximum ratings notes: 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. 2. maximum dc voltage on input/output pins is vcc+0.3v which, dur ing transitions, may overshoot to vcc+2.0v for periods < 20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as details in the operational sect ions of this data sheet. exposure to absolute maximum rating conditions for extend ed periods may affect reliability. v cc command i/o buffers & latches address register & decoders register control logic & high voltage generator global buffers output driver v ss command ce# re# we# cle wp# i/00 i/o7 or i/o15 v cc v ss ale pre flash array y-decoder cache register data register & s/a x-decoder 2gb: (2048m + 64m) bit 1gb: (1024m + 32m) bit ry/by# 512 mb: (512m + 16m) bit parameter symbol rating unit voltage on any pin relative to vss v in/out -0.5 to vcc + 0.5 v v cc -0.5 to + 2.5 storage temperature t stg -65 to +150 o c operating temperature t opr 0 to +70 (commercial) -40 to +85 (industrial) -25 to +85 (wireless) o c temperature under bias t bias -65 to 125 o c short circuit current i os 5ma
14 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 7. ordering information the order number is formed by a valid combinations of the following: 7.1 valid combinations valid combination list configurations planned to be sup ported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. see the mcp ornand data sheet for further package details. 3. model numbers 50 and 51 must use 2-bit detection, 1-bit correc tion for applications that require 100% error-free read perform ance. 4. model numbers 50 and 51 may have up to 2% invalid blocks. 5. model numbers 50 and 51 have a boot block (block 0 is valid upon shipment and error-free through 1000 cycles). s30ms 01g p 25 b f w 00 2 packing type 0= tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number (3) (4) 00 = x8; ecc-free 01 = x16; ecc-free 50 = x8; ecc-required with boot block 51 = x16; ecc-required with boot block temperature range w = wireless (?25c to +85c) package material set a = standard f = pb-free package type t = thin small outline package b = ball-grid array package speed option serial read access time 25 = 25 ns process technology p = 90 nm mirrorbit technology flash density 01g= 1gb 512= 512mb product family s30ms = 1.8 volt -only, nand interface flash memory valid combinations base ordering part number speed option package type, material, and temperature range model number packing type package type s30ms01gp s30ms512p 25 taw, tfw 00, 01, 50, 51 0, 3 (note 1) tsop-48
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 15 data sheet (preliminary) 8. electrical specifications 8.1 absolute maximum ratings notes: 1. minimum dc voltage is ?0.6 v on input/output pins. during transit ions, this level may undershoot to ?2.0 v for periods <30 ns . 2. maximum dc voltage on input/output pins is v cc +0.3 v which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for exten ded periods may affect reliability. 8.2 capacitance (ta = 25c, f = 1 mhz) notes: 1. test conditions t a = 25c, f = 1.0 mhz 2. sampled, not 100% tested. 8.3 valid blocks valid blocks are fully erased when the device is shipped fr om the factory. to identify blocks that are invalid at the time of shipment, the system must read the lowest address in the firs t two pages of the spare area. if a non-blank data pattern is read from either of these two addresses, the block is invalid. 8.4 recommended dc operating conditions parameter symbol rating unit voltage on any pin relative to vss v in/out ?0.5 to v cc + 0.5 v v cc ?0.5 to + 2.5 storage temperature t stg ?65 to +150 c operating temperature t opr ?25 to +85 (wireless) c temperature under bias t bias ?65 to +125 c short circuit current i os 5ma parameter symbol parameter description test condition typ. max. unit c in input capacitance v in = 0 ?10pf ?10pf c in2 ce# pin input capacitance v in = 0 ? 17 pf c in3 we# pin input capacitance v in = 0 ? 32 pf c out output capacitance v out = 0 ?10pf ?10pf parameter symbol parameter description density model number min. max. unit n vb number of valid blocks 512mb 50, 51 502 512 blocks 00, 01 512 512 blocks 1gb 50, 51 1004 1024 blocks 00, 01 1024 1024 blocks parameter symbol parameter description min. typ. max. unit v cc power supply voltage 1.7 1.8 1.95 v v ss power supply voltage 0 0 0 v
16 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 8.5 dc characteristics notes: 1. v ih can overshoot to v cc +0.4 v for durations of 20 ns or less. 2. v il can undershoot to ?0.4 v for durations of 20 ns or less. parameter symbol parameter description test conditions min. typ. max. unit i cc1 v cc active read current (average during read cycle) t rc = 25 ns, i out = 0 ma ?4045ma i cc2 v cc current during data transfer from memory cell array to page buffer ??4045ma i cc3 v cc current during data output t rc = 25 ns ? 10 20 ma i cc4 program current (standard mode) ? ? 60 75 ma i cc5 erase current (standard mode) ? ? 60 75 ma i sb1 stand-by current (ttl) ce# = v ih , wp# = pre# = v il ?? 1ma i sb2 stand-by current (cmos) ce# = v cc ?0.2 v, wp# = pre# = 0.2 v all other pins = -0.1 v ?1060a i li input leakage current v in = 0 to v cc , v cc = v cc max ??1a i lo output leakage current v out = 0 to v cc , v cc = v cc max ??1a v ih (note 1) input high voltage v cc - 0.4 ? v cc + 0.2 v v il (note 2) input low voltage ? ?0.3 ? 0.4 v v oh output high voltage level i oh = ?100 a, v cc = v cc min v cc - 0.1 ? ? v v ol output low voltage level i ol = 100 a, v cc = v cc min ??0.1v i ol output low current (ry/by#) v ol = 0.1 v 2 4 ? ma
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 17 data sheet (preliminary) 8.6 ac characteristics 8.7 ac test conditions parameter symbols description min. max. unit t cls cle setup time -1 ? ns t clh cle hold time 8 ? ns t cs ce# setup time 0 ? ns t ch ce# hold time 8 ? ns t wp write pulse width 25 ? ns t als ale setup time -1 ? ns t alh ale hold time 8 ? ns t ds data setup time 15 ? ns t dh data hold time 8 ? ns t wc write cycle time 40 ? ns t wh we# high hold time 10 ? ns t ww wp# high to we# low 100 ? ns t rr ready to re# falling edge 20 ? ns t rw ready to we# falling edge 20 ? ns t rp read pulse width 17 ? ns t rc read cycle time 25 ? ns t rea re# access time ? 17 ns t cr ce# to re# time 10 ns t ar ale to re# time 10 ns t clr cle to re# time 10 ns t oh data output hold time 5 ? ns t rhz re# high to output high impedance ? 15 ns t chz ce# high to output high impedance ? 15 ns t reh re# high hold time 8 ? ns t ir output high impedance to re# falling edge 0 ? ns t rhw re# high to we# low 30 ? ns t whc we# high to ce# low 30 ? ns t whr we# high to re# low 60 ? ns t r full page data transfer from memory cell array to register ? 25 s partial page data transfer from memory cell array to register ? 8 t rpre full page data transfer to register during power on read ? 50 s t wb we# high to busy ? 100 ns t rst device resetting time (read/program/erase) ? 1/1/15 s operating range v cc 1.7 v to 1.95 v input level 0.0 to v cc input comparison level v cc /2 output data comparison level v cc /2 load capacitance (c l ) 30 pf transition time (t t ) (input rise and fall times) 5 ns
18 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 8.8 program and erase characteristics notes: 1. one programming cycle per segment. refer to page program on page 30 for more information. 2. first cache programming of a sequence. 3. following cache programming of a sequence - second page and following pages. 4. typical program and erase times assume the following conditions: 25c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 5. under worst case conditions of 90c, v cc =1.70 v, 100,000 cycles. 9. timing diagrams figure 9.1 command input cycle timing diagram symbol parameter min. typ. (note 4) max. (note 5) unit t cbsy1 dummy busy time for cache programming (first 15h) (note 2) ?0.40.8s t cbsy2 dummy busy time for cache programming (next 15h) (note 3) ?0.84.4ms t prog page programming time ? 0.8 4.4 ms t pprog partial page programming time ? 260 1400 s n number of programming cycles on same page (note 1) ??8 t berase block erasing time ? 50 150 ms t cls cle ale i/o : v il or v ih ce# we# t clh t cs t ch t wp t als t alh t ds t dh
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 19 data sheet (preliminary) figure 9.2 address input cycle timing diagram figure 9.3 data input cycle timing diagram col. add2 : v ih or v il t dh t ds cle t wh t wp col. add1 t wc ale i/o row add1 row add2 ce# we# t clh t cls t ch t cs t alh t als : v ih or v il t wh t wp t wc t dh t ds d in 0 d in 1 ale cle i/o d in 2111 (x8) t ch t cs 1055 (x16) ce# we# t clh t cls t alh t als
20 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 9.4 serial read cycle timing diagram figure 9.5 status read cycle timing diagram t rc ce# re# i/ox t rp t reh t rea t oh t oh t rr t cr dout0 dout1 doutn ce# don't care t rhz t ch t chz ale# cle# 70h ce# re# i/ox ry/by# cle we# t clr t cls t cs t clh t wp t ch t cr t whc t whr t oh t rhz t ds t dh status output trea t ir : v ih or v il t chz t oh
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 21 data sheet (preliminary) figure 9.6 read cycle timing diagram figure 9.7 column address change in read cycle timing diagram (1/2) 30h row add2 row add1 col. add2 col. add1 i/o t cs t cls t clh t ch t wc t als t alh we# cle ale re# t dh t ds t alh t clr t r t wb t als t rc t rr t cr column address a data out from col. add. a 00h d out a d out a+1 page address p t ar ce# ry/by# t rea t clr i/o t cs t cls t clh t ch t wc t als t alh t r cle ale t dh t ds column address a t alh t wb tals t rc t rea t cr t rr page address p page address p column address a 00h 30h d out a d a+1 d out a+n a part a part b row add2 row add1 col. add2 col. add1 t ar ce# we# re# ry/by# out
22 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 9.8 column address change in read cycle timing diagram (2/2) figure 9.9 program operation timing diagram i/o t cs t cls t clh t ch 05h t wc t als t alh cle ale t dh t ds column address b e0h t alh t als t rea d out a + n t rhw page address p column address b t rc t clr t cr t ir d out b+n' d out b+1 d out b a we# col. add1 col. add2 part a part b ce# re# ry/by# t cls t cls t als t ds t dh cle ale : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t prog t wb t alh t als d in0 a d in1 d in 2111 (x8) 10h 70h status output 80h 1055 (x16) row add2 row add1 col. add2 col. add1 column address a ce# we# re# ry/by# t rw page address p
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 23 data sheet (preliminary) figure 9.10 block erase timing diagram notes: 1. if i/o 0 = 0 , then the erase is successful. if i/o0 = 1 , then there is an error in the erase. 2. only the block address part of the row address bytes are used; page address is ignored. figure 9.11 cache program operation timing diagram note: ce#, cle, and ale are don?t care. t cs 60h cle ale : v ih or v il t cls t clh t cls t ds t dh t als : do not input da ta while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy read status command erase s tart command status output t alh row add2 row add1 ce# we# re# ry/by# note 2 note 1 ? ? c e# cl e ry /by# w e# a le r e# 8 0 h d i n n d i n 1 5 h m s e rial d at a i n put c om m an d s erial i nput p ro g r a m t cb s y t wb tw c ? ? ? ? c o m m an d ( d u m m y ) d i n n d in 1 0 h tcbsy2 tw b ? ? ? i / o pr o gr a m c o nf ir m c om m an d ( tr u e ) 8 0h 7 0 h m i /o x co l a d d 1 col ad d2 r ow a d d 1 ro w add 2 co l a d d 1 co l a d d2 r o w a d d1 r o w a dd2 page address column add ress page addr ess col umn ad dre ss
24 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 9.12 page duplicate program timing diagram note: ce#, cle, and ale are don?t care. 9.1 id read figure 9.13 id read operation timing diagram note: ce#, cle, and ale are don?t care. ce# cle ry/by# we# ale re# 00h 70h i/o 0 85h column address read status command i/o 0 =0 s u c c e s s f u l p ro g ra m i/o 0 =1 e rror in p rogram tp r og tw b twc ? busy tw b tr busy ? 10h page duplicate date input c ommand 35h column address page address data 1 data n ? ? i/o x col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 page address 90h 00h 01h 2nd byte cle ce# we# ale re# i/o t cls t cs t cls t cs t alh t cr t ar t ch t als t alh t ds t dh t rea address input maker code device code t ch : v ih or v il 3rd byte 4th byte 5th byte
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 25 data sheet (preliminary) note: in x16, i/o15 - i/o8 = 00h table 9.1 id byte settings summary byte description hex data 1st byte maker code 01h 2nd byte device code 1st byte 512 mb (x8) 81h 512 mb (x16) 91h 1 gb (x8) a1h 1 gb (x16) b1h 3rd byte device code 2nd byte model numbers 50 and 51 (ecc required) 00h model numbers 00 and 01 01h 4th byte block size, simultaneous programmed pages, rfu 00h 5th byte page size, spare size, rfu 22h table 9.2 4th id byte description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 block size: 128 kbytes x xxxx000 block size: 512 kbytes x xxxx001 block size: 2048 kbytes x xxxx010 number of simultaneously programmed pages 1x x x 0 0 x x x 2x x x 0 1 x x x 4x x x 1 0 x x x 8x x x 1 1 x x x table 9.3 5th id byte description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size: 512 kbytes x x x x x 0 0 0 page size: 1024 kbytes x x x x x 0 0 1 page size: 2048 kbytes x x x x x 0 1 0 page size: 4096 kbytes x x x x x 0 1 1 page size: 8192 kbytes x x x x x 1 0 0 spare size: 0 bytes x x 0 0 0 x x x spare size: 8 bytes x x 0 0 1 x x x spare size: 16 bytes x x 0 1 0 x x x spare size: 32 bytes x x 0 1 1 x x x spare size: 64 bytes x x 1 0 0 x x x
26 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 10. schematic cell layout and address assignment the program operation works on page units while the erase operation works on block units. 10.1 array organization figure 10.1 array organization a page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. ? 1 page = 2112 bytes ? 1 block = 2112 bytes x 64 pages = (128k + 4k) bytes ? 1gb density = 2112 bytes x 64 pages x 1024 blocks table 10.1 shows a summary of the addressing for the memory array components. an address is read through the i/o port over four consecutive clock cycles, as shown in table 10.2 and table 10.3 . the notes for table 10.2 and table 10.3 are listed below table 10.3 . table 10.1 memory addressing key density bus width row address column address blocks block addres s page address in block main/spare area main page segment main colum n addres s spare page segment spare colum n addres s 1gb x8 a 27 :a 18 a 17 :a 12 a 11 (0=main, 1=spare) a 10 :a 9 a 8 :a 0 a 5 :a 4 a 3 :a 0 1024 1gb x16 a 26 :a 17 a 16 :a 11 a 10 (0=main, 1=spare) a 9 :a 8 a 7 :a 0 a 4 :a 3 a 2 :a 0 1024 512 mb x8 a 26 :a 18 a 17 :a 12 a 11 (0=main, 1=spare) a 10 :a 9 a 8 :a 0 a 5 :a 4 a 3 :a 0 512 512 mb x16 a 25 :a 17 a 16 :a 11 a 10 (0=main, 1=spare) a 9 :a 8 a 7 :a 0 a 4 :a 3 a 2 :a 0 512 table 10.2 (1gb) x 8 device 1gbit i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 l (note 1) l (note 1) l (note 1) l (note 1) 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 64 8 i/o for x8 16i/o for x16 64 pages = 1 block i/o7 i/o0 2048 2112 bytes 1gb device 64k pages 1024 blocks 512mb device 32k pages 512 blocks
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 27 data sheet (preliminary) notes: 1. l = v il. 2. a0 to a11:column address (12 bits for 2,112 bytes). a12 to a27: row address, consists of: a12 to a17: page address in block (6 bits for 64 pages). 3. a18 to a27: block address (1 gb device: a18 to a27, 10 bits for 1024 blocks; 512mb device: a18 to a26, 9 bits for 512 blocks. ) notes: 1. l = v il. 2. a0 to a1 0 :column address (11 bits for 1,056 words) 3. a11 to a26: row address, consists of: a11 to a16: page address in block (6 bits for 64 pages). a17 to a26: block address (1 gb device: a 17 to a 26 : 10 bits for 1024 blocks; 512mb device: a17 to a25: 9 bits for 512 blocks.) table 10.3 (512mb) x8 addressing 512mb i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 l (note 1) l (note 1) l (note 1) l (note 1) 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 l (note 1) table 10.4 (1gb) x 16 addressing 1gb i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 ? i/o15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l (note 1) 2nd cycle a 8 a 9 a 10 l (note 1) l (note 1) l (note 1) l (note 1) l (note 1) l (note 1) 3rd cycle a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 l (note 1) 4th cycle a 19 a 20 a 21 a 22 a 23 a 24 a 25 a 26 l (note 1) table 10.5 (512) x 16 addressing 512mb i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 ? i/o15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l (note 1) 2nd cycle a 8 a 9 a 10 l (note 1) l (note 1) l (note 1) l (note 1) l (note 1) l (note 1) 3rd cycle a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 l (note 1) 4th cycle a 19 a 20 a 21 a 22 a 23 a 24 a 25 l (note 1) l (note 1)
28 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 11. operation mode: logic and command tables the operation modes such as program, erase, read, an d reset are controlled by the thirteen different command operations shown in table 11.2 on page 28 . address input, command input and data input/output are controlled by the cle, ale, ce#, we #, re# and wp# signals, as shown in table 11.1 . notes: 1. h: v ih , l: v il , x: v ih or v il 2. wp# should be biased to cmos high or cmos low for standby. notes: 1. random data input/output can be executed in a page or 1/4 page. 2. input of a command other than those specified in table 11.2 is prohibited. stored data may be corrupted if an unknown command is entered during the command cycle. 3. during the busy state, input commands are restricted to 70h and ffh. table 11.1 operation table cle ale ce# we# re# pre wp# mode hll h x x read mode command input l h l h x x address input (4 clock cycles) l l x h h x x during read (busy) l l l h x x sequential read & data output hll h x h program mode command input l h l h x h address input (4 clock cycles) l l l h x h data input x x x x x x h during program (busy) x x x x x x h during erase (busy) x x x x x x l write protect xxh x x 0 v/v cc 0 v/v cc stand-by table 11.2 command table function 1st cycle 2nd cycle command accepted during busy state page read 00h 30h no partial page read 00h 31h no read for page duplicate 00h 35h no id read 90h ? no page program 80h 10h no cache program 80h 15h no page duplicate program 85h 10h no data input for column address change 85h ? no read for column address change 05h e0h no block erase 60h d0h no reset ffh ? yes status read 70h ? yes
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 29 data sheet (preliminary) notes: 1. h = v ih 2. l = v il 3. x = v ih or v il 12. device operation 12.1 read mode there are two types of read operat ions: random read and serial page read. the device defaults to read mode after power-up or a reset or may be initiated by writing 00h-30h to the command register along with four address cycles. a partial page read may be initiate d by writing 00h-31h to the command register along with the four address cycles. the ran dom data read is enabled by a page or partial page address change. the addressed page of data is loaded into the page register and the completion of the loading process is detected by polling the ry/by# pin or reading the stat us register. once the data is loaded into the page register, it may be read by clocking re#. the hi gh to low transition of the re# signal outputs data sequentially, starting with the first selected column address and ending with the last selected column address. subsequent reads will output the last column address data. see figure 12.1 for timing details. the device may output random data in a page instead of the consecutive sequential data upon entering the random data output command. the column address of the next data to be read can be changed to the address which follows the random data output command. the random data output command may be issued multiple times, but must be within the same page. figure 12.1 read mode table 11.3 read mode operation status operation cle ale ce# we# re# i/o0 to i/o15 power output select l l l h l data output active output deselect l l x h h high impedance active standby x x h x x high impedance standby cle 00h ale i/o busy 30h page address p column address a a page address p start-address input cell array select page p a n x8 x16 a+1 a+2 : n=1056 words : n=2112 bytes ce# we# re# ry/by# a data transfer operation from the cell array to the page buffer starts on the rising edge of we# in the 30h command input cycle (after the address information has been latched). the device is in busy state during this transfer period. after the transfer period the device returns to ready state. serial data can be output synchronously with the re# clock from the start pointer designated in the address input cycle.
30 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 12.2 column address read 12.2 page program the page program command sequence ( figure 12.3 ) enables the system to write a page of data into the device. this command sequence is used for page programming and partial page programming in both the main area and the spare area of the memory array. partial page programming allows the system to write multiple times to the same page by dividing the page into eight segments. the address sc heme for the segments is described in table 12.1 . once a segment is programmed, any subsequent wr ites to the same segme nt without erase will cause the initial data in the segment to become inva lid. the data written duri ng the second write will be valid. the device also supports random data programming within a page by using the random data input command (85h). random data input requires the command to be entered between column addresses during the page program command cycle. once the new column addre ss is entered, the system can continue the page program command cycle by entering the page address and th e data. the page prog ram confirm command (10h) initiates the programming operation. s tart-address input select page p a cle 00h ale i/o col. a page p a? busy page a 30h 05h e 0h col. a? a a? page p col. a s tart from col. a s tart from col. a' a+1 a+2 a+3 a?+1 a?+2 a?+3 a?+4 ce# we# re# ry/by# cell array during the serial data output from the register the column address can be changed by inputting a new column address using the 05h and e0 commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. table 12.1 page segments x8 x16 data area 512 bytes x 4 segments / page 512 bytes x 4 segments / page 1st segment column address 0 to 511 column address 0 to 255 2nd segment column address 512 to 1023 column address 256 to 511 3rd segment column address 1024 to 1535 column address 512 to 767 4th segment column address 1536 to 2047 column address 768 to 1023 spare area 16 bytes x 4 segments / page 16 bytes x 4 segments / page 1st segment column address 2048 to 2063 column address 1024 to 1031 2nd segment column address 2064 to 2079 column address 1032 to 1039 3rd segment column address 2080 to 2095 column address 1040 to 1047 4th segment column address 2096 to 2111 column address 1048 to 1055
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 31 data sheet (preliminary) once the program operation starts, the read status regi ster command may be enter ed to read the status register. the system controller c an detect the completion of a program cycle by monito ring the ry/by# output, or the status bit (i/o6) of the status register. only the read status command and reset command are valid while programming is in progress. when the pa ge program is complete, the write status bit (i/o0) may be verified. the internal write verify detects only errors for 1s that are not successfully programmed to 0s . the command register remains in read status comm and mode until another valid command is written to the command register. figure 12.3 page program once the serial input command 80h is input, t he only acceptable commands are the programming commands 10h, 85h or the reset comm and ffh. if any other input comm and is used, the program operation is not performed and the device must be reset. figure 12.4 serial input command sequence note: if xxx is a command other than 10h, 85h, or ffh, the operation does not execute. when this occurs, the reset command ( ffh ) must be entered to return the device to a valid state. cle 80h ale i/o page p col. a din 10h 70h din din din data program data input read and verification ce# we# re# ry/by# the data is transferred (programmed) from the page buffer to the selected page on the rising edge of we# following input of the 10h command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. 80 xxx 10
32 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 12.3 cache program cache program is a double buffer scheme for faster prog ramming. the cache buffer size is identical to the page buffer size (i.e. 2112byte (x8) or 1056word (x16) da ta registers). data may be written into the cache register while other data stor ed in the page buffer are programmed into the memory array. after writing the first set of data up to 2112byte (x8) or 1056word (x16) into the cache register, the cache program command (15h) must be entered instead of t he standard page program command (10h) in order to free up the cache register and start the internal program o peration. to transfer data from the cache register to the data register, the device remains in the busy state for a short period of time (t cbsy ) and has its cache register ready for the next data-input while the internal programming starts with the data loaded into the data register. the read status command (70h) may be issued to verify that the cache register is ready by polling the cache-busy status bit (i/o6). pass /fail status of the previous page is available upon the return to the ready state. when the next set of data is input with the cache program command, t cbsy is affected by the progress of pending internal programming. the programmi ng of the cache register is initiated only when the pending program cycle is finished a nd the data register is available for the transfer of data from the cache register. the status bit (i/o5) for internal ready/bu sy may be polled to identify the completion of internal programming. if the system monitors the progress of programming with ry/by# only, the last page of the target programming sequence must be programmed with page program command (10h). alte rnatively, if the last page to be programmed is accomplished using the cache program command (15h), status bit (i/o5) must be polled to verify that the last program is ac tually finished before starting other operations. following the cache program command (15h), the pass/ fail status information is available as follows: 1. i/o1 returns the status of the previous page (when ready or when the i/o6 bit is changing to a 1 ). 2. i/o0 returns the status of the current page (upon true ready, or when the io5 bit is changing to a 1 ). 3. i/o0 and i/o1 may be read together. figure 12.5 cache program note: since programming the last page does not employ caching, the program time has to be that of page program. however, if the previ ous program cycle with the cache data has not finished, the actual prog ram cycle of the last page is initiated only after completio n of the previous cycle, which can be expressed as the following formula: t prog = program time of last page + program time of the (last -1) page - (program command time + data loading time of last page). 80h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h tcbsy1 tcbsy2 tcbsy2 tprog 70h address & data input* 15h 80h 70h tcbsy1 address & data input 15h status output 80h 70h tcbsy2 address & data input 15h status output 80h tcbsy2 address & data input 15h 80h tcbsy2 address & data input 15h 70h status output 70h status output status output check i/o5 for internal ready/busy check i/o0,1 for pass/fail check i/o1 for pass/fail i/ox col add1,2 & row add1,2 col add1,2 & row add1,2 col add1,2 & row add1,2 data data data col add1,2 & row add1,2 data col add1,2 & row add1,2 data col add1,2 & row add1,2 data col add1,2 & row add1,2 data col add1,2 & row add1,2 data ry/by# ry/by#
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 33 data sheet (preliminary) 12.4 page duplicate program the page duplicate program is configured to quickly an d efficiently rewrite data stored in one full page (no partial page) without utilizing an external memory. since the time-consuming serial access and re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the block also needs to be co pied to the newly assigned free block. a page duplicate program operation is performed by first initiating a read operation with command 35h and the address of the source which then duplicates the whole 2112byte (x8) or 1056word (x16) data into the internal data buffer. as soon as the device is ready, the program confi rm command (10h) is required to actually begin the programming operation to the address of the destination page. once the page duplicate program is finished, any additional partial page programming into the copied pages is prohibited before erasure. the data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in figure 12.6 on page 33 . page data duplicates directly to another page in a block. figure 12.6 page duplicate program operation figure 12.7 page duplicate program operation with random data input 12.5 block erase the block erase process starts with the block eras e setup command 60h, followed by two cycles of row address, followed by the block erase execute command d0h. note that the page address part of the row address is ignored. the block erase operation starts on the rising edge of we# after the erase start command d0h which follows the erase setup command 60h. this two-cycle process for erase operations acts as an extra layer of protection from accidental erasure of data due to exte rnal noise. the device automat ically executes the erase and verify operations. figure 12.8 block erase 12.6 write operation status the device provides a ry/by# output pin and status register bits to determine the status of a write operation. the status register bits can be used to determine which stage the write operation is in. 00h add.(4cycles) i/o0 pass 85h 70h fail tprog add.(4cycles) tr source address destination address 35h 10h i/ox col. add1,2 & row add1,2 col. add1,2 & row add1,2 ry/by# 00h add.(4cycles) 85h 70h tprog add.(4cycles) tr source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox col. add1,2 & row add1,2 col. add1,2 & row add1,2 col add1,2 ry/by# 60 ry/by# i/o pass fail d0 70 erase status command status read command busy block address input: 2 cycles
34 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 12.7 status read the device contains a status register which may be read to find out whether a prog ram or erase operation is completed, and whether the program or erase oper ation completed successfully. after writing a 70h command to the command register, a read cycle outputs the content of the stat us register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. the control by two lines allows the system to poll the progress of each device in multiple device connection even if the ry/by# pins are common wired. re# or ce# does not have to be toggled for update status. refer to table 12.2 for specific status register definitions. the command register remains in stat us read mode until further commands are issued. therefore, if the status register is read during a random re ad cycle, the read command (00h) should be given before starting read cycles. the status register clears after another valid command is ente red, excluding a status read. an application example with multiple devices is shown in figure 12.9 . notes: 1. true ready/busy represents internal program operation status which is being executed in cache program mode. 2. i/os defined ?not use? are recommended to be masked out when read status in being executed. figure 12.9 multiple devices if the ry/by# pin signals from multiple devices are wired together as shown in figure 12.9 , the status read function can be used to determine the status of each individual device. table 12.2 status output table i/o during program or erase operation page program block erase cache program read definition i/o0 reserved pass/fail pass/fail pass/fail(n) reserved 0 = pass; 1 = fail i/o1 reserved reserved reserv ed pass/fail(n-1) reserved 0 = pass; 1 = fail i/o2 reserved normal normal normal normal 0 = normal i/o3 reserved reserved reserved reserved reserved i/o4 reserved reserved reserved reserved reserved i/o5 busy true ready/busy ready/busy true ready/busy ready/busy 0 = busy; 1 = ready i/o6 busy cache ready/busy ready/b usy cache ready/busy ready/busy 0 = busy; 1 = ready i/o7 reserved write protect write protect write protect write protect 0 = protected; 1 = unprotected device(1) ce(1)# device(2) ce(2)# device(n) ce(n)# ale cle we# re# n i/on ry/by#
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 35 data sheet (preliminary) figure 12.10 status read timing application example 12.8 reset the reset mode aborts all operations in progress includ ing read, erase and program. for example, in the case of a program or erase operation the internally gene rated voltage is discharged to 0 volts and the device enters standby. any attempted memory data alteration is invalidated if interrupted by a reset command. the response to an ffh reset command input during the various device operations is shown in figure 12.11 to figure 12.15 . figure 12.11 reset (ffh) command input during programming note: the reset time (t rst ) is not the same for program, erase, and read operations. figure 12.12 reset (ffh) command input during erasing note: the reset time (t rst ) is not the same for program, erase, and read operations. cle we# ale i/o ry/by# 70h status on device n status on device 1 ce1# cen# re# 70h busy v il internal v pp 10 ff 00 ry/by# t rst (see note) 80 internal erase voltage d0 ff 00 ry/by# t rst (see note)
36 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 12.13 reset (ffh) command input during a read operation note: the reset time (t rst ) is not the same for program, erase, and read operations. figure 12.14 reset (ffh) command during operations other than program, erase, or read note: the reset time (t rst ) is not the same for program, erase, and read operations. figure 12.15 status read command (70h) input after a reset 00 ff 00 ry/by# t rst (see note) 00 ff 00 ry/by# t rst (see note) ff 70 ff 70 i/o status: ready/busy busy i/o status: ready/busy ready ry/by# ry/by#
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 37 data sheet (preliminary) 13. application notes 13.1 power on/off sequence a nd power-on read enable 13.1.1 power-on/off sequence the wp# signal is useful for protecting against da ta corruption at power-on/off. the following timing sequence is necessary. the wp# signal may be negated any time after the v cc reaches 1.6 v and the ce# signal is kept high in power up sequence. a reset command issued during the power up sequence is ignored. figure 13.1 power-on/off sequence for stable operation, it is recommended to start accessing the device 200 s after v cc becomes 1.6 v. there is no restriction regarding the v cc ramp rate. 13.1.2 power-on read enable power on read is a feature for ce rtain architectures that requires the system to read data from page 0 without a command sequence on power-up. to enable power on read, pre must be tied to v cc to ensure a simultaneous ramp rate. please refer to the following waveform. page zero data is read from the memory array to the page buffer without any command and addr ess input sequence following power-on. the function will be performed when v cc attains about 1.6 v. the pre pin contro ls activation of auto-page read function. serial access may begin after t rpre . a reset command issued during the power-on read enable is acceptable. figure 13.2 shows the timing diagram. don?t care ce# re# cle, ale wp# 0 v v cc 1.7 v don?t care 1.6 v operation don?t care don?t care we# t pre 10 s 1.7 v 1.6 v ry/by# don?t care don?t care
38 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 13.2 power-on auto -read enable 13.2 status read during a read operation figure 13.3 status read during a read operation the device status can be read by inputting the status read command 70h in read mode. once the device is set to status read mode by a 70h command, the device will not return to read mode. however, when the read command 00h is input during [a], the status mode is reset and the device returns to read mode. in this case, data output starts automatically from address n and address input is unnecessary. a pull-up resistor must be used for termination because t he ry/by# buffer consists of an open drain circuit. don?t care ce# re# cle, ale wp# 0 v v cc 1.7 v don?t care 1.6 v operation don?t care don?t care we# t rpre 10 s 1.7 v 1.6 v ry/by# don?t care don?t care pre# command 00 70 00 [a] by# ry/ re# we# ce# address n status read command input status read data output 30 2nd cycle of the read command
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 39 data sheet (preliminary) figure 13.4 ry/by#: termination for th e ready/busy pin (ry/by#) 13.2.1 when wp# signal goes low holding the wp# pin low protects the device during powe r transitions. if wp# is low during the program/erase command input period, the device is protected and doe s not enter the program/erase operation. if wp# is high during the program/erase command input period, t he device can execute the program/erase operation. the user should keep the wp# pin either high or low during the complete command & program/erase operation. the operations are enabled and disabl ed as shown in the following timing diagrams: t f read y v cc vol t r voh vol busy vol=0.1v, voh= vcc - 0.1v vcc max - vol iol + il 1.95 v 3 ma + il r = = device vcc vcc r cl ry/by# vss this data may vary from device to device. we recommend that you use this data as a reference when selecting a resistor value.
40 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) figure 13.5 wp# signal?low we# t ww (100 ns min) 80 10 wp# by# ry/ d in [enable programming] we# t ww (100 ns min) 80 10 wp# by# ry/ d in [disable programming] we# t ww (100 ns min) 60 d0 wp# by# ry/ d in [enable erasing] we# t ww (100 ns min) 60 d0 wp# by# ry/ d in [disable erasing]
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 41 data sheet (preliminary) 13.2.2 ce# don?t care feature ce# does not need to be continuously asserted ac ross command and address write operations or during busy periods as was required by some ea rlier generation nand interface devices.
42 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) 14. revision history section description revision a (january 3, 2005) initial release revision a1 (may 16, 2005) performance characteristics table updated specifications. program and erase performance table updated entire table connection diagrams updated all diagrams block diagram corrected the ry/by# command dc characteristics table added standard and low power mode specifications to: i cc4 and i cc5 ac characteristics and recommended operating conditions table updated min. specifications for: t wp , t ds , and t dh program and erase characteristics table updated entire table id definition table updated entire table x8 array organization updated the figure x16 array organization updated the figure when wp# signal goes low updated section revision a2 (july 6, 2005) front page added 100% valid blocks statement ordering information revised and corrected various parameters added model numbers 02 and 03 removed industrial temperature grade dc characteristics table revised various parameters ac characteristics table revised and added various timing parameters program and erase characteristics ta b l e revised t cbsy1 and t cbsy2 corrected p/e specification byte tables removed 7th id byte table updated device id bytes 2, 3, 4, and 5 pin names removed v io pin removed ry/by#1 and ry/by#2 command table added pipeline read?full page no additional requests command pipeline read revised feature description and timing diagram reset after power-on removed section timing diagrams corrected multiple timing diagrams capacitance table updated the entire table valid blocks table updated the entire table power-on read enable added section and timing diagrams revision a3 (september 12, 2005) title added ecc-free connection diagrams updated entire diagram program and erase characteristics changed va rious program and erase specifications distinctive characteristics changed data retention value schematic cell layout and address assignment added the memory addressing key table format converted data sheet to standard format spansion xtreme mode updated and added content revision a4 (november 11, 2005)
june 13, 2007 s30ms-p_00_a8 s30ms-p ornand tm flash family 43 data sheet (preliminary) global removed specifications removed 2 gb specifications distinctive characteristics changed write performance value status read output table updated table reset timing diagrams changed the t rst values power on/off sequence updated section revision a5 (december 16, 2005) valid blocks table updated table dc characteristics removed the specifications for low power mode serial read cycle timing diagram corrected reset pin signal revision a6 (march 22, 2006) xtreme mode command definitions defined wp# state during block status read ordering revisions added model number desc riptions to include boot block product programming clarified notes on program/erase characteristics table program and erase characteristics changed the dummy busy time during cache programming ac characteristics changed the timing for partial page da ta transfer to memory cell array to register (t r ) power on read enable clarified power on read operation revision a7 (august 4, 2006) global removed all references to xtreme mode performance characteristics updated tables connection diagrams updated diagram capacitance added the capacitance values for wp# and ce# pins valid blocks updated table dc characteristics changed i cc4 and i cc5 ac characteristics changed read cycle timing parameters changed timing for command latch enable and address latch enable program and erase characteristics updated table timing diagrams corrected page transfer timing on page duplicate program timing diagram ordering information update models numbers for parts that require ecc revision a8 (june 13, 2007) page programming page programming clarification section description
44 s30ms-p ornand tm flash family s30ms-p_00_a8 june 13, 2007 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2005-2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners.

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